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Figure 14.3. EBI Non-multiplexed 8-bit Data, 8-bit Address Write Operation
WRSETUP
(0, 1, 2, ...)
WRSTRB
(1, 2, 3, ...)
WRHOLD
(0, 1, 2, ...)
EBI_AD[ 15:8]
EBI_AD[ 7:0]
ADDR[ 7:0]
DATA[ 7:0]
Z
Z
EBI_CSn
EBI_WEn
14.3.2 16-bit Address Mode
In this mode, 16-bit address and 16-bit data is supported, which requires the utilization of a latch. The
16-bit address and 16-bit data bits are multiplexed on the EBI_AD lines. An illustration of such a setup
is shown in Figure 14.4 (p. 136) . This mode is set by programming the MODE field in the EBI_CTRL
register to D16A16ALE.
Note
In this mode the 16-bit address is organized in 2-byte chunks at memory addresses aligned
to 2-byte offsets. Consequently, the LSB of the 16-bit address will always be 0. In order to
double the address space, the 16-bit address is internally shifted one bit to the right so that
the LSB of the address driven into the EBI_AD bus, i.e. the EBI_AD[0]-bit, corresponds to
the second least significant bit of the address, i.e. ADDR[1]. At the external device, the LSB
of the address must be tied either low or high in order to create a full address.
Figure 14.4. EBI Address Latch Setup
EBI
(EFM32)
EBI_AD
Latch
ALE
ADDR
External
Async.
Device
DATA
Control
At the start of the transition the address is output on the EBI_AD lines. The Latch is controlled by the
ALE (Address Latch Enable) signal and stores the address. Then the data is read or written according
to operation. Read and write signals are shown in Figure 14.5 (p. 136) and Figure 14.6 (p. 137)
respectively.
Figure 14.5. EBI Multiplexed 16-bit Data, 16-bit Address Read Operation
ADDRSETUP
(1, 2, 3, ...)
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
RDHOLD
(0, 1, 2, ...)
EBI_AD[ 15:0]
ADDR[ 15:0]
Z
DATA[ 15:0]
Z
EBI_ALE
EBI_CSn
EBI_REn
2011-04-12 - d0001_Rev1.10
136
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